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Features
* * * *
Speech Circuit with Anti-clipping Tone-ringer Interface with DC/DC Converter Speaker Amplifier with Anti-distortion Power-supply Management (Regulated, Unregulated) and a Special Supply for Electret Microphone * Voice Switch * Interface for Answering Machine and Cordless Phone
Applications
* * * * *
Feature Phone Answering Machine Fax Machine Speaker Phone Cordless Phone
Programmable Telephone Audio Processor U4091BM-N
Benefits
* No Piezoelectric Transducer for Tone Ringing Necessary * Complete System Integration of Analog Signal Processing on One Chip * Very Few External Components
Description
The programmable telephone audio processor U4091BM-N is a linear integrated circuit for use in feature phones, answering machines and fax machines. It contains the speech circuit, tone-ringer interface with DC/DC converter, sidetone equivalent and ear-protection rectifiers. The circuit is line-powered and contains all components necessary for signal amplification and adaptation to the line. The U4091BM-N can also be supplied via an external power supply. An integrated voice switch with loudspeaker amplifier enables hands-free or loudhearing operation. With an anti-feedback function, acoustic feedback during loudhearing can be reduced significantly. The generated supply voltage is suitable for a wide range of peripheral circuits.
Rev. 4666B-CORD-08/04
Figure 1. Block Diagram
Speech circuit
Voice switch
Audio amplifier
Clock Data Reset
Serial bus DTMF Tone ringer
MCU
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VL
2 38 17 TXACL 15 STBAL
43
44 39 42 9 10
1
8
5
Figure 2. Detailed Block Diagram
Power supply
16 12
AGATX
4
3
MICRO AGARX TXA
11 30 Offset canceler DTMF/ melody Filter MUX
MIC
V MIC
40
Offset canceler
22 21
Ringing power converter
19 20
LIDET VMP RFDO
AGCO LRX DTMF
AMPB
ADC
V RING
AGC
AGCI EPO RXLS AMREC LTX
Switch matrix
optional
41 REG POR
7
6 SACL SA 14 13 35 AFS control
RA
DIV.
1/8/16/32
18
BIDIR serial bus 34 37 36 33 31 32 24 25 23
OSC.
3.58 MHz
26
28 29 27
C
U4091BM-N
RECO1
MICO
V MP
3
Pin Configuration
Figure 3. Pinning SSO44
RECIN TXACL MIC3 MIC2 MIC1 RECO2 RECO1 IND VL SENSE GND VB SAO2 SAO1 VMPS VMP VMIC TSACL VRING IMPA COSC SWOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 U4091BM 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 STRC STC STO AMREC AMPB MICO IMPSW TLDT INLDT INLDR TLDR CT BNMT BNMR ADIN ES
28 OSCOUT 27 RESET 26 25 24 23 OSCIN SDA SCL INT
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Pin Description
Pin Symbol
Function Receive amplifier input(1) Time constant adjustment for transmit anti-clipping Microphone input for hands-free operation Input of symmetrical microphone amplifier with high common-mode rejection ratio Input of symmetrical microphone amplifier with high common-mode rejection ratio Output of the receive amplifier Output of the receive amplifier, also used for sidetone network The internal equivalent inductance of the circuit is proportional to the value of the capacitor at this pin. A resistor connected to ground may be used to adjust the DC mask. Positive supply-voltage input to the device in speech mode Input for sensing the available line current Ground, reference point for DC and AC signals Unstabilized supply voltage for speech network Negative output of speaker amplifier (push-pull only) Positive output of speaker amplifier (single ended and push-pull operation) Unregulated supply voltage for the microcontroller (via series regulator to VMP) Regulated output voltage for supplying the microcontroller (typically 3.3 V/6 mA in speech mode) Reference node for microphone amplifier, supply for electret microphones Time constant for speaker amplifier anti-clipping Input for ringer supply Input for adjusting the ringer input impedance 70-kHz oscillator for ringing power converter Output for driving the external switch resistor Interrupt line for serial bus Clock input for serial bus Data line for serial bus Input for 3.58-MHz oscillator Reset output for the microcontroller Clock output for the microcontroller Input for external supply indication Input of A/D converter Output of background-noise monitor receive Output of background-noise monitor transmit Time constant for mode switching of voice switch Time constant of receive-level detector Input of receive-level detector Input of transmit-level detector Time constant of transmit-level detector Switch for additional line impedance
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Note:
RECIN TXACL MIC3 MIC2 MIC1 RECO2 RECO1 IND VL SENSE GND VB SAO2 SAO1 VMPS VMP VMIC TSACL VRING IMPA COSC SWOUT INT SCL SDA OSCIN RESET OSCOUT ES ADIN BNMR BNMT CT TLDR INLDR INLDT TLDT IMPSW
1. The protection device at Pin RECIN is disconnected.
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Pin Description
Pin Symbol
Function Microphone preamplifier output Input for playback signal of answering machine Output for recording signal of answering machine Output for connecting the sidetone network Input for sidetone network Input for sidetone network
39 40 41 42 43 44 Note:
MICO AMPB AMREC STO STC STRC
1. The protection device at Pin RECIN is disconnected.
DC Line Interface and Supply-voltage Generation
The DC line interface consists of an electronic inductance and a dual-port output stage which charges the capacitors at VMPS and VB. The value of the equivalent inductance is given by:
2 x RSENSE x C IND x ( R DC x R30 ) L = -----------------------------------------------------------------------------------------( R DC + R 30 )
The U4091BM-N contains two identical series regulators which provide a supply voltage VMP of 3.3 V suitable for a microprocessor. In speech mode, both regulators are active because VMPS and VB are charged simultaneously by the DC line interface. The output current is 6 mA. The capacitor at VMPS is used to provide the microcomputer with sufficient power during long line interruptions. Thus, long flash pulses can be bridged or an LCD display can be turned on for more than 2 seconds after going on-hook. When the system is in ringing mode, VB is charged by the on-chip ringing power converter. In this mode, only one regulator is used to supply VMP with maximum 3 mA.
Supply Structure of the Chip
A main benefit of the U4091BM is the easy implementation of various applications due to the flexible system structure of the chip. Possible applications: * * * * Group listening phone Hands-free phone Phones which feature ringing with the built-in speaker amplifier Answering machine with external supply
The special supply topology for the various functional blocks is illustrated in Figure 4 on page 7. There are four major supply states: 1. Speech condition: In speech condition, the system is supplied by the line current. If the LIDET-block detects a line voltage above approximately 2 V, the internal signal VLON is activated. This is detected via the serial bus, all the blocks which are needed have to be switched on via the serial bus. For line voltages below 2 V, the switches remain in quiescent state as shown in the diagram. 2. Power down (pulse dialing): When the chip is in power-down mode (Bit LOMAKE), e.g., during pulse dialing, all internal blocks are disabled via the serial bus. In this condition, the voltage regulators and their internal band gap are the only active blocks.
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3. Ringing: During ringing, the supply for the system is fed into VB via the Ringing Power Converter (RPC). Normally, the speaker amplifier in single-ended mode is used for ringing. The frequency for the melody is generated by the DTMF/Melody generator. 4. External supply: In an answering machine, the chip is powered by an external supply via pin VB. The answering machine connections can be directly made to U4091BM-N. The answering machine is connected to the pin AMREC. For the output AMREC, an AGC function is selectable via the serial bus. The output of the answering machine will be connected to the pin AMPB, which is directly connected to the switching matrix. This enables the signal to be switched to every desired output. Figure 4. Supply Generator
VL R SENSE 10 C 1 F IND R + R 300 k V 220 F + + 5.5 V 3.3 V VMP 47 F VB 5.5 V VMPS 470 F
Ringing Power Converter (RPC)
The RPC transforms the input power at VRING (high voltage/low current) into an equivalent output power at VB (low voltage/high current) which is capable of driving the lowohmic loudspeaker. The input impedance at VRING is adjustable from 3 k to 12 k by RIMPA (ZRING = RIMPA/100) and the efficiency of the step-down converter is approximately 65%. The U4091BM-N provides an output signal for the microcontroller. This output signal is always double the value of the input signal (ringing frequency). It is generated by a current comparator with hysteresis. The levels for the on-threshold are programmable in 16 steps, the off-level is fixed. Every change of the comparator output generates a high level at the interrupt output INT. The information can then be read out by means of a serial bus with either normal or fast read mode. The block RFD is always enabled. Table 1. Threshold Level
RINGTH[0:3] 0 15 Step VRING 7V 22 V 1V
Ringing Frequency Detector (RFD)
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Clock Output Divider Adjustment
The Pin OSCOUT is a clock output which is derived from the crystal oscillator. It can be used to drive a micro-controller or another remote component and thereby reduces the number of crystals required. The oscillator frequency can be divided by 1, 8, 16, 32. During power-on reset, the divider will be reset to 1 until it is changed by setting the serial bus. Table 2. Clock Output
CLK[0:1] 0 1 2 3 Divider 1 8 16 32 Frequency 3.58 MHz 447 kHz 224 kHz 112 kHz
Serial Bus Interface
The circuit is controlled by an external microcontroller through the serial bus. The serial bus is a bi-directional system consisting of a one-directional clock line (SCL) which is always driven by the microcontroller, and a bi-directional data-signal line. It is driven by the microcontroller as well as from the U4091BM-N (see Figure 24 on page 37). The serial bus requires external pull-up resistors as only pull-down transistors (Pin SDA) are integrated.
WRITE
The data is a 12-bit word: A0 - A3: address of the destination register (0 to 15) D0 - D7: content of the register The data line must be stable when the clock is high. Data must be shifted serially. After 12 clock periods, the write indication is sent. Then, the transfer to the destination register is (internally) generated by a strobe signal transition of the data line when the clock is high.
READ
There is a normal and a fast-read cycle. In the normal read cycle, the microcontroller sends a 4-bit address followed by the read indicator, then an 8-bit word is read out. The U4091BM-N drives the data line. The fast read cycle is indicated by a strobe signal. With the following two clocks the U4091BM-N reads out the status bits RFDO and LIDET which indicate that a ringing signal or a line signal is present (see Figure 5 on page 11, Figure 6 on page 11 and Figure 7 on page 11).
DTMF Dialing
The DTMF generator sends a multi-frequency signal through the matrix to the line. The signal is the result of the sum of two frequencies and is internally filtered. The frequencies are chosen from a low and a high frequency group. The circuit conforms to the CEPT recommendation concerning DTMF option. Three different levels for the low level group and two different pre-emphasis (2.5 dB and 3.5 dB) can be chosen by means of the serial bus (rec. T/CF 46-03). Attention: In high gain mode distortion can occur, if AGATX is high and DC mask is low.
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Melody - Confidence Tone Generation
Melody/confidence tone frequencies are given in Table 3. The frequencies are provided at the DTMF input of the switch matrix. A sinusoidal wave, a square wave or a pulsed wave can be selected by the serial bus. A square signal means the output is half of the frequency cycle high and half low. A pulsed signal means between the high and low phases are high impedance phases of 1/6 of the period. Table 3. Status of Melody Generating
Decimal 0 1 2 3 4 5 6 7 DTMFM[0:2] 000 001 010 011 100 101 110 111 Status DTMF generator OFF Confidence tone melody on (sinus) Ringer melody (pulse) Ringer melody (square signal) DTMF (mid level) DTMF (low level) DTMF (high level) -
Table 4. DTMF Frequencies
Decimal 0 1 2 3 DTMFF[0:1] in DTMF Mode 00 01 10 11 Frequency 697 770 852 941 Error (%) -0.007 -0.156 0.032 0.316
Table 5. DTMF Frequencies
Decimal 0 1 2 3 DTMFF[2:3] in DTMF Mode 00 01 10 11 Frequency 1209 1336 1477 1633 Error (%) -0.110 0.123 -0.020 -0.182
Table 6. DTMFF4 in DTMF Mode
Pre-emphasis Selection 0 1 Level 2.5 dB 3.5 dB
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Table 7. DTMF and Melody Frequencies
Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 DTMFF [0:4] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 f Hz 440.0 466.2 493.9 523.2 554.4 587.3 622.3 659.3 698.5 740.0 784.0 830.0 880.0 932.3 987.8 1046.5 1108.7 1174.7 1244.5 1318.5 1396.9 1480.0 1568.0 1661.2 1760.0 1864.6 1975.5 2093.0 2217.5 2349.3 2663.3 2983.0 Tone/ Name a
1 1
Error (%) -0.008 -0.016 -0.003 0.014
DTMF Freq. 697 770 852 941 697 770 852 941 697 770 852 941 697 770 852 941 697 770 852 941 697 770 852 941 697 770 852 941 697 770 852 941
DTMP Freq. 1209 1209 1209 1209 1336 1336 1336 1336 1477 1477 1477 1477 1633 1633 1633 1633 1209 1209 1209 1209 1336 1336 1336 1336 1477 1477 1477 1477 1633 1633 1633 1633
Key 1 4 7 * 2 5 8 0 3 6 9 # A B C D 1 4 7 * 2 5 8 0 3 6 9 # A B C D
b
h1 c2 des d
2 2
0.018 -0.023 -0.129 0.106 -0.216
es2 e2 f
2 2
ges g2 as a b
-0.222 0.126 -0.169 0.288 -0.014 -0.004 -0.335
2
2 2
h2 c3 des d
3 3
-0.355 -0.023 -0.129 0.106 -0.214
es3 e3 f
3 3
ges g3 as a b
-0.222 0.126 -0.241 -0.302 -0.014 0.665 0.367
3
3 3
h3 c
4 4
des d
4
0.387 0.771 -----
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Figure 5. Write Cycle
Write cycle
CLOCK
DATA
D7
D6
D5
D4
D3
D2
D1
D0
A3
A2
A1
A0
R/W=0
Data from P
Strobe from P
Figure 6. Normal Read Cycle
Normal read cycle
CLOCK
DATA
A3
A2
A1
A0
R/W=1 Strobe from P
D7
D6
D5
D4
D3
D2
D1
D0
Data from P
Data from U4091B
Figure 7. Fast Read Cycle
Fast read cycle
CLOCK
DATA Strobe from P
D7=IZC D6=IVE
Data from U4091B
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Table 8. Names and Functions of the Serial Registers
Register Group No. Name Description Status
R0
Enables
R0B0 R0B1 R0B2 R0B3 R0B4 R0B5 R0B6 R0B7
ENRING ERX ETX ENVM ENMIC ENSTBAL MUTE ENRLT ENSACL ENSA ENSAO ENAM ENAGC free free FOFFC I1O1 I1O2 I1O3 I1O4 I1O5 I2O1 I2O2 I2O3 I2O4 I2O5 I3O1 I3O2 I3O3 I3O4 I3O5 I4O1 I4O2 I4O3 I4O4
Enable ringer Enable receive part Enable transmit part Enable VM-generator Enable microphone Enable side tone Muting earpiece amplifier Enable POR low threshold Enable anti-clipping for speaker amplifier Enable speaker amplifier and AFS Enable output stage speaker amplifier Enable answering machine connections Enable AGC for answering machine 0 0 0 0 0 0 0 Speed up offset canceller Switch on MIC/LTX Switch on MIC/SA Switch on MIC/EPO Switch on MIC/AMREC Switch on MIC/AGCI Switch on DTMF/LTX Switch on DTMF/SA Switch on DTMF/EPO Switch on DTMF/AMREC Switch on DTMF/AGCI Switch on LRX/LTX Switch on LRX/SA Switch on LRX/EPO Switch on LRX/AMREC Switch on LRX/AGCI Switch on AMPB/LTX Switch on AMPB/SA Switch on AMPB/EPO Switch on AMPB/AMREC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1
1
1
R1
Enables
R1B0 R1B1 R1B2 R1B3 R1B4 R1B5 R1B6 R1B7
R2
Matrix
R2B0 R2B1 R2B2 R2B3 R2B4 R2B5 R2B6 R2B7
R3
Matrix
R3B0 R3B1 R3B2 R3B3 R3B4 R3B5 R3B6 R3B7
R4
Matrix
R4B0 R4B1 R4B2
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Table 8. Names and Functions of the Serial Registers (Continued)
Register Group No. Name Description Status
R4B3 R4B4 R4B5 R4B6 R4B7 R5 AGATX MICLIM R5B0 R5B1 R5B2 R5B3 R5B4 R5B5 R5B6 R5B7 R6 Shut down Sidetone R6B0 R6B1 R6B2 R6B3 R6B4 R6B5 R6B6 R6B7 R7 Sidetone AGARX R7B0 R7B1 R7B2 R7B3 R7B4 R7B5 R7B6 R7B7 R8 EARA Line imp. R8B0 R8B1 R8B2 R8B3 R8B4 R8B5 R8B6
I4O5 I5O1 I5O2 I5O3 I5O4 EAFS AGATX0 AGATX1 AGATX2 MICHF DBM5 MIC0 MIC1 SD free SL0 SL1 LF0 LF1 LF2 LF3 P0 P1 P2 P3 P4 AGARX0 AGARX1 AGARX2 EA0 EA1 EA2 EA3 EA4 IMPH LOMAKE
Switch on AMPB/AGCI Switch on AGCO/LTX Switch on AGCO/SA Switch on AGCO/EPO Switch on AGCO/AMREC Enable AFS block Gain transmit AGA LSB Gain transmit AGA Gain transmit AGA MSB Select RF-microphone input Maximum transmit level for anti-clipping Gain microphone amplifier LSB Gain microphone amplifier MSB Shut down
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Slope adjustment for side tone LSB Slope adjustment for side tone MSB Low frequency adjustment for side tone LSB Low frequency adjustment for side tone Low frequency adjustment for side tone Low frequency adjustment for side tone MSB Pole adjustment for sidetone LSB Pole adjustment for side tone Pole adjustment for side tone Pole adjustment for side tone Pole adjustment for side tone MSB Gain receive AGC LSB Gain receive AGC Gain receive AGC MSB Gain earpiece amplifier LSB Gain earpiece amplifier Gain earpiece amplifier Gain earpiece amplifier Gain earpiece amplifier MSB Line impedance selection (1 = 1 k) Short circuit during pulse dialing
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Table 8. Names and Functions of the Serial Registers (Continued)
Register Group No. Name Description Status
R8B7 R9 AFS R9B0 R9B1 R9B2 R9B3 R9B4 R9B5 R9B6 R9B7 R10 SA R10B0 R10B1 R10B2 R10B3 R10B4 R10B5 R10B6 R10B7 R11 ADC R11B0 R11B1 R11B2 R11B3 R11B4 R11B5 R11B6 R11B7 R12 DTMF R12B0 R12B1 R12B2 R12B3 R12B4 R12B5 R12B6 R12B7 R13 CLK RTH TM R13B0 R13B1 R13B2
AIMP AFS0 AFS1 AFS2 AFS3 AFS4 AFS5 AFS4PS free SA0 SA1 SA2 SA3 SA4 SE LSCUR0 LSCUR1 ADC0 ADC1 ADC2 ADC3 NWT SOC ADCR MSKIT DTMFF0 DTMFF1 DTMFF2 DTMFF3 DTMFF4 DTMFM0 DTMFM1 DTMFM2 CLK0 CLK1 RTH0
Switch for additional external line impedance AFS gain adjustment LSB AFS gain adjustment AFS gain adjustment AFS gain adjustment AFS gain adjustment AFS gain adjustment MSB Enable 4-point sensing
0 0 0 0 0 0 0 0 0
Gain speaker amplifier LSB Gain speaker amplifier Gain speaker amplifier Gain speaker amplifier Gain speaker amplifier MSB Speaker amplifier single-ended mode Speaker amplifier charge-current adjustment LSB Speaker amplifier charge-current adjustment MSB Input selection ADC Input selection ADC Input selection ADC Input selection ADC Network tuning Start of ADC conversion Selection of ADC range Mask for interrupt bits DTMF frequency selection DTMF frequency selection DTMF frequency selection DTMF frequency selection DTMF frequency selection Generator mode selection Generator mode selection Generator mode selection Selection clock frequency for C Selection clock frequency for C Ringer threshold adjustment LSB
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Table 8. Names and Functions of the Serial Registers (Continued)
Register Group No. Name Description Status
R13B3 R13B4 R13B5 R13B6 R13B7 R14 TM CLOR R14B0 R14B1 R14B2 R14B3 R14B4 R14B5 R14B6 R14B7 R15 CLOT R15B0 R15B1 R15B2 R15B3 R15B4 R15B5 R15B6 R15B7
RTH1 RTH2 RTH3 TME0 TME1 TME2 TME3 free CLOR0 CLOR1 CLOR2 CLOR3 CLOR4 free free free CLOT0 CLOT1 CLOT2 CLOT3 CLOT4
Ringer threshold adjustment Ringer threshold adjustment Ringer threshold adjustment MSB Test mode enable (low active) Test mode enable (high active) Test mode enable (high active) Test mode enable (low active)
0 0 0 0 0 0 0 0
Adjustment for calculated receive log amp LSB Adjustment for calculated receive log amp Adjustment for calculated receive log amp Adjustment for calculated receive log amp Adjustment for calculated receive log amp MSB
0 0 0 0 0 0 0 0
Adjustment for calculated transmit log amp LSB Adjustment for calculated transmit log amp Adjustment for calculated transmit log amp Adjustment for calculated transmit log amp Adjustment for calculated transmit log amp MSB
0 0 0 0 0
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Power-on Reset
To avoid undefined states of the system when it is powered on, an internal reset clears the internal registers. The system (U4091BM-N + microcontroller) is woken up by any of the following conditions: * * * * VMP > 2.75 V and VB > 2.95 V and line voltage (VL) or ringer (VRING) or external supply (ES)
The power-down of the circuit is caused by a shut-down sent by the serial bus (SD = 1), low-voltage reset or by the watchdog function (see Figure 9 on page 17, Figure 10 on page 18 and Figure 11 on page 18).
Watchdog Function
To avoid the system operating the microcontroller in a wrong condition, the circuit provides a watchdog function. The watchdog has to be retriggered every second by triggering the serial bus (sending information to the IC or other remote components at the serial bus). If there has been no bus transmission for more than one second, the watchdog initiates a reset. The watchdog provides a reset for the external microcontroller, but does not change the U4091BM-N's registers.
Acoustic Feedback Suppression
Acoustical feedback from the loudspeaker to the hands-free microphone may cause instability of the system. The U4091BM-N has a very efficient feedback-suppression circuit which offers a 4-point- or alternatively a 2-point-signal-sensing topology (see Figure 8 on page 17). Two attenuators (TXA and SAI) reduce the critical loop gain via the serial bus either in the transmit or in the receive path. The overall loop gain remains constant under all operating conditions. The LOGs produce a logarithmically-compressed signal of the TX- and RX-envelope curve. The AFSCON block determines whether the TX or the RX signal has to be attenuated. The voice-switch topology can be selected by the serial bus. In 2-point-sensing mode, AFSCON is controlled directly by the LOG outputs.
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Figure 8. Basic System Configurations
MICRO TXA MICO STO CTU RTU TLDT INLDT LOG BNMT LOG CALCT CTLO CBNMT AGATX
BNM Mode control BNM Line
AGARX LOG CALCR CT CCT AFSCON SA SAI DTD RECO2 BNMR CBNMR TLDR CRLO LOG INLDR RRU CRU RECO1 HV
Figure 9. Power-on Reset (Line)
Line LID IVDD OSCOUT ton
VMP Reset t rt - t on = 4.5 ms t on = start-up oscillator
trt
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Figure 10. Power-on Reset (Ringing)
VRING VB IVDD VMP OSCOUT Reset t rt
t on
Figure 11. Power-on Reset (Low Voltage Reset)
Line LID VMP LVI LVR
LVI Reset OSCOUT
Dial-Tone Detector
The dial-tone detector is a comparator with one side connected to the speaker amplifier input and the other to VM with a 35-mV offset (see Figure 12 on page 21). If the circuit is in idle mode, and the incoming signal is greater than 35 mV (25 mVrms), the comparator's output will change thus disabling the receive idle mode. This circuit prevents the dial tone (which would be considered as continuous noise) from fading away as the circuit would have the tendency to switch to idle mode. By disabling the receive idle mode, the dial tone remains at the normally expected full level. This circuit distinguishes speech (which consists of bursts) from background noise (a relatively constant signal level). There are two background-noise monitors, one for the receive path and the other for the transmit path. The receive background-noise monitor is operated on by the receive level detector, while the transmit background noise monitor is operated on by the transmit level detector (see Figure 13 on page 21). They monitor the background noise by storing a DC voltage representative of the respective noise levels in capacitors at CBNMR and CBNMT. The voltages at these pins have slow rise times (determined by the internal current source and an external C), but fast decay times. If the signal at TLDR (or TLDT) changes slowly, the voltage at BNMR (or BNMT) will remain more positive than the voltage at the non-inverting input of the monitor's output comparator. When speech is present, the voltage at the non-inverting input of the comparator will rise more quickly than the voltage at the inverting input (due to the burst characteristic of speech), causing its output to change. This output is sensed by the mode-control block.
Background Noise Monitors
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4-point Sensing
In 4-point sensing mode, the receive- and the transmit-sensing path include additional CLOGs (Calculated Logarithmical amplifiers). The block MODECON compares the detector output signals and decides whether receive-, transmit- or idle mode has to be activated. Depending on the mode decision, MODECON generates a differential voltage to control AFSCON. The MODECON block has seven inputs: * * * * * * * The output of the transmit log (LOGT) the comparison of LOGT, CLOGR The output of the receive clog (CLOGR) - designated I1 The output of the transmit clog (CLOGT) the comparison of CLOGT, LOGR The output of the receive log (LOGR) - designated I2 The output of the transmit background-noise monitor (BNMT) - designated I3 The output of the receive background-noise monitor (BNMR) - designated I4 The output of the dial-tone detector
The differential output (AFST, AFSR) of the block MODECON controls AFSCON. The effect of I1-I4 in Table 9. Table 9. Mode Decision for Signal Sensing
Input Output
I1 T T R R T T R R Note:
I2 T R T R T R T R
I3 S Y Y X N N N X
I4 X Y Y S X N N N
Mode Transmit Change mode Change mode Receive Idle Idle Idle Idle
X = do not care; Y = I3 and I4 are not both noise.
LOGT > CLOGR LOGT < CLOGR LOGR < CLOGT LOGR > CLOGT BNMT detects speech BNMT detects noise BNMR detects speech BNMR detects noise
I1 = T I1 = R I2 = T I2 = R I3 = S I3 = N I4 = S I4 = N
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Term Definitions
1. Transmit means the transmit attenuator is fully on, and the receive attenuator is at maximum attenuation. 2. Receive means the receive attenuator is fully on, and the transmit attenuator is at maximum attenuation. 3. In Idle mode, the transmit and receive attenuator are at half of their maximum attenuation. - Change mode means both the transmit and receive speech are present in approximately equal levels. The attenuators are quickly switched (30 ms) to the opposite mode until one speech level dominates the other. Idle means speech has ceased in both transmit and receive paths. The attenuators are then slowly switched (1.5 s) to idle mode.
-
4. Switching to full transmit or receive modes from the idle mode is done at a fast rate (30 ms).
Summary of Truth Table
1. The circuit will switch to transmit mode if: - - - - - Both transmit level detectors sense higher signal levels than the respective receive level detectors and The transmit background-noise monitor indicates the presence of speech Both receive level detectors sense higher signal levels than the respective transmit level detectors, and The receive background-noise monitor indicates the presence of speech the level detectors disagree on the relative strengths of the signal levels, and at least one of the background-noise monitors indicates speech. Both speakers are quiet (no speech present), or When one speaker speech level is continuously overridden by noise at the other speaker's location
2. The circuit will switch to receive mode if:
3. The circuit will switch to the reverse mode if:
4. The circuit will switch to idle mode when: - -
The time required to switch the circuit between transmit, receive and idle is determined by internal current sources and the capacitor at Pin CT. A diagram of the CT circuitry is shown in Figure 14 on page 21. It operates as follows: * * CCT is typically 4.7 F. To switch to transmit mode, ITX is turned on (IRX is off), charging the external capacitor to -240 mV below VM. (An internal clamp prevents further charging of the capacitor.) To switch to receive mode, IRX is turned on (ITX is off), increasing the voltage on the capacitor to +240 mV with respect to VM. To switch to reverse mode, the current sources ITX, IRX are turned off, and the current source IFI is switched on, discharging the capacitor to VM. To switch to idle mode, the current sources ITX, IRX, IFI are turned off, and the current source ISI is charging the capacitor to VM.
* * *
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Figure 12. Dial Tone Detector
IN + 35 mV V M DTD OUT I4 to mode control
Figure 13. Background Noise Monitor
V B BNMR (BNMT) TLDR (TLDT) + 56 k 33 k V M 36 mV + + I 4 (I ) 3 1 F
Figure 14. Generation of Control Voltage (CT) for Mode Switching
CT C CT I RX 10 m I A TX 10 m I FI A I SI
AFS control
to attenuators
Control circuit
4 I 1-4
Dial tone det. V M V M
21
4666B-CORD-08/04
Figure 15. Block Diagram Hands-free Mode U4091BM-N 2-point Signal Sensing
TXA MICRO LOG
AFS control
Line
LOG SA SAI
Figure 16. Block Diagram Hands-free Mode U4091BM-N 4-point Signal Sensing
TXA MICRO LOGT CLOGT
BNMT
Mode control
BNMR
Line
CLOGR CT CCT AFS control SA SAI DTD
LOGR
22
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U4091BM-N
Analog-to-Digital Converter ADC
This circuit is a 7-bit successive approximation analog-to-digital converter in switched capacitor technique. An internal band gap circuit generates a 1.25-V reference voltage which is the equivalent of 1 MSB. 1LSB = 19.5 mV. The possible input voltage at ADIN is 0 to 2.48 V. The ADC needs an SOC (Start Of Conversion) signal. In the High phase of the SOC signal, the ADC is reset. Then, 50 s after the beginning of the Low phase of the SOC signal, the ADC generates an EOC (End Of Conversion) signal which indicates that the conversion is finished. The rising edge of EOC generates an interrupt at the INT output. The result can be read out by the serial bus. Voltages higher than 2.45 V have to be divided. The signal connected to the ADC is determined by 4 bits: ADC0, ADC1, ADC2 and ADC3. TLDR/TLDT measuring is possible relative to a preceding reference measurement. The current range of IL can be doubled by ADCR. If ADCR is High, S has the value 0.5, otherwise S = 1. The source impedance at ADIN must be lower than 250 k. Accuracy: 1 LSB + 3% Figure 17. Timing of ADC
SOC 50 s
EOC
Figure 18. ADC Input Selection
IL x 20mV/(1mA x S) ADIN 0.4 x VB 0.4 x VMPS 0.4 x VMP 8 x (TLDR-REF) 8 x (TLDT-REF) 0.4 x SAO1 0.4 x OFF1 0.4 x OFF2 0.4 x OFF3 EOC MSB BIT5 BIT4 SOC
ADC
BIT3 BIT2 BIT1 LSB
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4666B-CORD-08/04
Table 10. Input Selection AD Converter
Decimal ADC[1:4] Symbol Value
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Note:
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
OFF IL ADIN extern VB VMPS VMP TLDR TLDT free SAO1 Offcan1 Offcan2 Offcan3 free free free V4 = (2.5 V/0.4) x D/128 Atmel's internal use I1 = S x 127 mA x D/128 V2 = 2.5 V x D/128 (maximum 2.5 V) V3 = (2.5 V/0.4) x D/128 V4 = (2.5 V/0.4) x D/128 V5 = (2.5 V/0.4) x D/128 V6 = 8 x (Vp - Ref) x D/128 V7 = 8 x (Vp - Ref) x D/128
D = measured digital word (0 D 127) S = programmable gain 0.5 or 1 Vp = peak value of the measured signal
24
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Switch Matrix
The switch matrix has 5 inputs and 5 outputs. Every pair of I/Os except AGCO and AGCIN can be connected. The inputs and outputs used must be enabled. If 2 or more inputs are switched to an output, the sum of the inputs is available at the output. The inputs MIC and LRX have offset cancellers with a 3-dB corner frequency of 270 Hz. AMPB has a 60-k input impedance. The TXO output has a digitally-programmable gain stage with a gain of 2, 3 to 9 dB depending on AGATX0 (LSB), AGATX1, AGATX2 (MSB) and a first order low-pass filter with 0.5 dB damping at 3300 Hz and 3 dB damping at 9450 Hz. The outputs RXLS, EPO and AMREC have a gain of 0 dB. The offset at the outputs of the matrix is less than 30 mV. If a switch is open, the path has a damping of more than 60 dB. Figure 19. Switch Matrix Diagram
AGCO AMPB LRX DTMF MIC Offset canceller I5 I4 I3 I2 Offset canceller I1
AGC
Lowpass O5 O4 O3 O2 O1 2.9 dB LTX AMREC EPO RXLS AGATX0 AGATX1 AGATX2 TXO -10 dB STO
AGCI
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4666B-CORD-08/04
Table 11. Bits and Corresponding Switches
Register No. Name Description
R2
R2B0 R2B1 R2B2 R2B3 R2B4 R2B5 R2B6 R2B7
I1O1 I1O2 I1O3 I1O4 I1O5 I2O1 I2O2 I2O3 I2O4 I2O5 I3O1 I3O2 I3O3 I3O4 I3O5 I4O1 I4O2 I4O3 I4O4 I4O5 I5O1 I5O2 I5O3 I5O4
Switch on MIC/LTX Switch on MIC/RXLS Switch on MIC/EPO Switch on MIC/AMREC Switch on MIC/AGCI Switch on DTMF/LTX Switch on DTMF/RXLS Switch on DTMF/EPO Switch on DTMF/AMREC Switch on DTMF/AGCI Switch on LRX/LTX Switch on LRX/RXLS Switch on LRX/EPO Switch on LRX/AMREC Switch on LRX/AGCI Switch on AMPB/LTX Switch on AMPB/RXLS Switch on AMPB/EPO Switch on AMPB/AMREC Switch on AMPB/AGCI Switch on AGCO/LTX Switch on AGCO/RXLS Switch on AGCO/EPO Switch on AGCO/AMREC
R3
R3B0 R3B1 R3B2 R3B3 R3B4 R3B5 R3B6 R3B7
R4
R4B0 R4B1 R4B2 R4B3 R4B4 R4B5 R4B6 R4B7
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Side Tone System
Figure 20. Principle Circuit of Side Tone Balancing
LTX
8dB
LINE CK ZL
LRX
0-7dB
+ DIFF1 STO_DIFF AGARX
MOD
-10dB
RECIN
AMP1
STO
-10dB
9dB
AMP2
STOAMP
Sidetone balancing
STO 8.2 k
g
LF
P
STRC
CTO 33 nF SL STC
f
LF
P
SL
The Side Tone Balancing (STB) has the task of reducing the cross-talk from LTX (microphone) to LRX (earpiece) in the frequency range of 0.3 to 3.4 kHz. The LTX signal is converted into a current in the MOD block. This current is transformed into a voltage signal (LINE) by the line impedance ZL. The LINE signal is fed into the summing amplifier DIFF1 via capacitor CK and attenuator AMP1. On the other hand the LTX buffered by STOAMP drives an external low-pass filter (RST, CST). The external low-pass filter and the internal STB have the transfer function drawn in the STB box. The amplified STB-output signal drives the negative input of the summing block. If both signals at the DIFF1 block are equal in level and phase, we have good suppression of the LTX signal. In this condition, the frequency and phase response of the STB block will represent the frequency curve on line. In real life the line impedance ZL varies strongly for different users. To obtain good suppression with one application for all different line impedances, the STB function is programmable. The 3 programmable parameters are: 1. LF (gain at low frequency) LF has 15 programming steps of 0.5 dB LF(0) provides -2 dB gain, LF(15) provides 5.5 dB gain STO_DIFF(LF) = (-10 dB - 2 dB + 0.5 dB x LF + 9 dB) x LTX
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4666B-CORD-08/04
2. P (the pole position of the low-pass) The P adjustment has 31 steps. P(0) means the lowpass determined by the external application (RST, CST). The internally processed low-pass frequency is fixed by equation:
1 P f(P) = --------------------------------------------------- x 1.122 2 x x CST x RST
3. SL (sidetone slope; the pole frequency of the high-pass) The SL has 3 steps. SL(0) is a lower frequency of the high-pass. SL(3) is a higher frequency of the high-pass. With SL, can be influenced the suppression at high frequencies. Figure 21. Audio Frequency Signal Management U4091BM-N
-10dB
-3dB ... -10dB and 7dB (NWT)
Offset cancel
32dB -23dB
ST Sidetone balancing
7dB 0dB and 20dB (NWT)
SAO1
6dB
VL Line
Offset cancel
1dB steps
LRX
RXLS 1.5dB steps
Loudspeaker SAO2
26dB -3dB and -10dB (DTMF)
RECO1 Earpiece
DTMF < -34dBm/ -32dBm >
DTMF generator MIC1 Handset microphone MIC2 Intercom microphone Answering machine MIC3
0dB 6dB steps 0dB 30dB 12dB
Filter
7dB -48dB
DTMF < -24dBm/ -22dBm >
DTMF
EPO 1dB steps 9dB 2dB
Switching matrix
Offset cancel
MIC LTX
RECO2
VL
8dB 1dB steps MOD
Line
1dB steps
AMREC
0dB AMPB AMREC 0dB
AMPB
Answering machine
0dB
AGCO
AGCI
0dB
AGC
14578
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Absolute Maximum Ratings
Parameters Symbol Value Unit
Line current DC line voltage Maximum input current Junction temperature Ambient temperature Storage temperature Total power dissipation, Tamb = 60 C
IL VL IRING Tj Tamb Tstg Ptot
140 12 15 125 -25 to +75 -55 to +150 0.9
mA V mA
C C C
W
Thermal Resistance
Parameters Symbol Value Unit
Junction ambient SSO44
RthJA
70
K/W
Electrical Characteristics
f = 1 kHz, 0 dBm = 775 mVrms, IVMIC = 0.3 mA, IMP = 3 mA, RDC = 1.3 M, Tamb = 25C, Zear = 68 nF + 100 , RLS = 50 , ZM = 68 nF, resonator: f = 3.58 MHz, all bits in reset condition, unless otherwise specified.
Parameters DC Characteristics Test Conditions
Symbol Min. Typ. Max. Unit
DC voltage drop-over circuit
IL = 2 mA IL = 14 mA IL = 60 mA IL = 100 mA
VL
4.4 8.6
1.6 4.8 7.2 9.2
5.2 9.8
V V V V
Transmission Amplifier, IL = 14 mA, VMIC = 2 mV, MICG[0:1] = 2, AGATX[0:2] = 7 ERX = ETX = ENMIC = ENSTBAL = I1O1 = I3O3 = 1, (GT = 48 dB)
Transmit amplification Frequency response due to internal filters Gain change with current Gain deviation CMRR of microphone amplifier Input resistance of MIC amplifier Input resistance of MIC3 amplifier Gain difference between MIC1, MIC2 to MIC3 Distortion at line Maximum output voltage
MICG[0:1] = 2 AGATX[0:2] = 7 IL 14 mA, f = 1 kHz to 3.4 kHz IL = 14 mA to 100 mA Tamb = -10 C to +60 C
GT
GT GT GT
45.3 -1
46.5
47.7 0 0.5 0.5
dB dB dB dB dB k
CMRR Ri MICHF = 1 MICHF = 1 IL 14 mA, VL = 700 mVrms IL 19 mA, d < 5%, VMIC = 10 mV CTXA = 1 F, DBM5 = 0 DBM5 = 1 VMIC = 20 mV, MICG[0:1] = 3 Ri
GT
60 75
80 50 150 300 0.4 2
k dB % dBm dBm dBm
dt VLmax VLmax VMICOmax 1.8 4.8 3.0 6.0 -4.2
4.2 6.6
Note:
1. This is a space of time where the bus must be from data transmission and before a new transmission can be started
29
4666B-CORD-08/04
Electrical Characteristics (Continued)
f = 1 kHz, 0 dBm = 775 mVrms, IVMIC = 0.3 mA, IMP = 3 mA, RDC = 1.3 M, Tamb = 25C, Zear = 68 nF + 100 , RLS = 50 , ZM = 68 nF, resonator: f = 3.58 MHz, all bits in reset condition, unless otherwise specified.
Parameters Test Conditions
Symbol Min. Typ. Max. Unit
Noise at line phosphometrically weighted Anti-clipping: attack time release time Gain at low operating current
IL 14 mA, MICG[0:1] = 2 AGATX[0:2] = 7 CTXA = 1 F each 3 dB overdrive IL = 8 mA, IMP = 1 mA VMIC = 0.5 mV IVMIC = 300 A IL = 8 mA, IMP = 1 mA VMIC = 5 mV IVMIC = 300 A
no
- 73
- 70
dBmp
ta tr GT 45
2 80 48
ms ms dB
Distortion at low operating current
dt
5
%
Receiving Amplifier IL = 14 mA, VGEN = 300 mV, ERX = ETX = ENMIC = ENSTBAL = I1O1 = I3O3 = 1, SL[0:1] = 0, LF[0:3] = 1, P[0:4] = 31, AFS[0:5] = 54, AGARX[0:2] = 0
Adjustment range of receiving gain
Single ended, IL 14 mA, Mute = 1, EA[0:4] = 2 - 31 AGARX[0:2] = 0 - 7 Differential AGARX[0:2] = 0 EA[0:4] = 15 EA[0:4] = 31 IL 14 mA, f = 1 kHz to 3.4 kHz IL = 14 to 100 mA Tamb = -10 to +60 C IL 14 mA, VGEN = 11 Vrms EA[0:4] = 15 IL = 14 mA, I303 = 0 IL = 14 mA Zear = 68 nF + 100 EA[0:4] = 11 Zear = 100 EA[0:4] = 31 IL = 14 mA Zear = 68 nF + 100 EA[0:4] = 15 Z = 600 Each output against GND IL = 6.5 mA, IMP = 1 mA IM = 300 mA VGEN = 200 mV EA[0:4] = 21, ENMIC = ETX = I101 = 0
GR
-19
+17
dB
Receiving amplification
GR
GRF GR GR
-1 14.7 -1
0 15.7
1 16.7 0 0.5 0.5 3
dB dB dB dB dB Vrms dB
Frequency response Gain change with current Gain deviation Ear protection differential
EP
GR
MUTE suppression (earpiece disconnect from matrix) Output voltage d < 2% differential Maximum output current d < 2% Receiving noise phosphometrically weighted Side tone suppression Output resistance Gain at low operating current (receive only)
60
0.775 Iout 4
Vrms mAp - 79 - 76 dBmp dB 10
20 Ro
GR
-2
0
2
dB
Note:
1. This is a space of time where the bus must be from data transmission and before a new transmission can be started
30
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Electrical Characteristics (Continued)
f = 1 kHz, 0 dBm = 775 mVrms, IVMIC = 0.3 mA, IMP = 3 mA, RDC = 1.3 M, Tamb = 25C, Zear = 68 nF + 100 , RLS = 50 , ZM = 68 nF, resonator: f = 3.58 MHz, all bits in reset condition, unless otherwise specified.
Parameters Test Conditions
Symbol Min. Typ. Max. Unit
Distortion at low operating current Adjustment step: earpiece amplifier Adjustment step: AGARX Gain for DTMF signal AC impedance
IL = 6.5 mA, IMP = 1 mA IM = 300 A, EA[0:4] = 15, ENMIC = ETX = I101 = 0
EA[0:4] = 1 for EA[0:4] = 2 ... 31 AGARX[0:2] = 1
dR
5
%
0.8 0.8
1 1 -10
1.2 1.2
dB dB dB
AMPB AE RECO1/2 EA[0:4] = 1 IMPH = 0 IMPH = 1 Sum level, 600 , DTMFM[0:2] = 4 Sum level, 600 , DTMFM[0:2] = 5 Sum level, 600 , DTMFM[0:2] = 6 AGATX[0:2] = 1 600 , DTMFF4 = 0 DTMFF4 = 1 Zimpl Zimph 595 980
625 1030
655 1080

DTMF, IL = 14 mA, ETX = I201 = 1, AGATX[0:2] = 7, DTMFM[0:2] = 4, DTMFF[0:4] = 0
DTMF level at line (mid gain) DTMF level at line (low gain) DTMF level at line (high gain)
-5.1 -7.6
-3.6 -6.1
-2.1 -4.6
dBm dBm
-5.2 2 3
-3.7 2.5 3.5
-2.2 3 4
dBm dBm dBm
Pre-emphasis
Speaker Amplifier, Differential Mode AMPB SAO1/2 ENSACL = ENSA = ENSAO = ENAM = I4O2 = 1, SA[0:4] = 31, ERX = ETX = ENMIC = ENSTBAL = I1O1 = I3O3 = 1
Minimum line current for operation
ENAM = I4O2 = 0 SE = 0, I3O2 = 1 IMP 1 mA, VGEN = 300 mV VAMPB = 3 mV, IL = 15 mA, SA[0:4] = 31 SA[0:4] = 0
SA[0:4] = -1
ILmin
11
mA
Gain from AMPB to SAO
GSA
36 1.15
37 -5.5 1.35
38 1.55
dB dB
Adjustment step speaker amplifier Output power single ended
Load resistance: RLS = 50 , d < 5% VAMPB = 40 mV, SE = 1 IL = 15 mA IL = 20 mA Load resistance: RL = 50 , d < 5% VAMPB = 60 mV, SE = 0 VB = 5 V IL > 15 mA
PSA PSA
3
7 20
mW mW
Maximum output power differential
PSA
150
mW
Output noise (input AMPB open) phosphometrically weighted Gain deviation Note:
nSA IL = 15 mA Tamb = -10 to +60 C
GSA
240
mVpsoph dB
1
1. This is a space of time where the bus must be from data transmission and before a new transmission can be started
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4666B-CORD-08/04
Electrical Characteristics (Continued)
f = 1 kHz, 0 dBm = 775 mVrms, IVMIC = 0.3 mA, IMP = 3 mA, RDC = 1.3 M, Tamb = 25C, Zear = 68 nF + 100 , RLS = 50 , ZM = 68 nF, resonator: f = 3.58 MHz, all bits in reset condition, unless otherwise specified.
Parameters Test Conditions
Symbol Min. Typ. Max. Unit
Mute suppression
IL = 15 mA, VL = 0 dBm, VAMPB = 4 mV I4O2 = 0 IL = 15 to 100 mA IL = 15 mA f = 1 kHz to 3.4 kHz 20 dB overdrive ENSAO = 0, SE = 1 LSCUR[0:1] = 1 ENSAO = 0, SE = 0 LSCUR[0:1] = 1 ENSAO = 0, SE = 1 LSCUR[0:1] = 3 ENSAO = 0, SE = 0 LSCUR[0:1] = 3
VSAO
GSA GSA
-56 1 -1 2 170 -480 320 -400 400 -1.2 1.2 -320 480 -0.95 1.45 0
dBm dB dB ms ms A A mA mA
Gain change with current Gain change with frequency Attack time of anti-clipping Release time of anti-clipping Adjustment step of charge current Adjustment step of discharge current Charge current Pin SAO2 Discharge current Pin SAO2
tr tf
ICHA IDIS
-1.45 0.95
Microphone Amplifier, VB = 5 V, VMIC = 2 mV, VMIC3 = 2 mV, ENMIC = ENAM = I1O4 = 1, MICHF = 0
Gain MIC amp.: MIC1/2 AE AMREC
MICG[0:1] = 0 MICG[0:1] = 1 MICG[0:1] = 2 MICG[0:1] = 3
17.4 23.2 29.1 35.0 35.0 60 60
18.1 23.7 29.8 35.7 35.7
18.8 24.6 30.5 36.4 36.5
dB dB dB dB dB dB dB
MIC3 to AMREC Input suppression: MIC3 to MIC1/2 MIC1/2 to MIC3 Settling time offset-cancellers Settling time offset-cancellers in speed-up mode
MICHF = 1, MICG[0:1] = 3 MICG[0:1] = 0, MICHF = 0 MICHF = 1 5 , FOFFC = 0 5 , FOFFC = 1
9 1.8
12 2.4
ms ms
AGC for Answering Machine, AMPB to AMREC, ENAM = ENAGC = I4O5 = I5O4 = 1
Nominal gain Maximum output level Attack time Release time
VAMPB = 5 mV VAMPB = 50 mV, d< 5% 20 dB overdrive
23.5 240
25.5 300 1 45
27.5 360
dB mVp ms ms
Switching Matrix, VL = 0, VB = 5 V, ENAM = I4O4 = 1, VAMPB = 0.6 Vrms
Input impedance AMPB Gain AMPB to AMREC Note:
50 -0.7
60 -0.3
70 0.1
k dB
1. This is a space of time where the bus must be from data transmission and before a new transmission can be started
32
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U4091BM-N
Electrical Characteristics (Continued)
f = 1 kHz, 0 dBm = 775 mVrms, IVMIC = 0.3 mA, IMP = 3 mA, RDC = 1.3 M, Tamb = 25C, Zear = 68 nF + 100 , RLS = 50 , ZM = 68 nF, resonator: f = 3.58 MHz, all bits in reset condition, unless otherwise specified.
Parameters Test Conditions
Symbol Min. Typ. Max. Unit
Maximum input level AMPB Maximum output level AMREC Offset Mute switching matrix
I4O5 = I5O4 = 1, I4O4 = 0 I4O4 = 1 I4O4: 1 to 0 I4O4 = 0
VAMREC
600 VB600 mV 30 60
mV VPP mV dB
Power-on Reset VL = 0, VMP = 3.3 V, VB = 5 V, U4091 in Power-down Mode
Power-on reset by ES VB high, VMP threshold Power-on reset by ES VMP high, VB threshold
Low-voltage Interrupt VL = 0, VMP = 3.3 V, VB = 0 V
VB = 4 V, ES = 4 V, rise VMP until RESET goes to low VMP = 3 V, ES = 4 V, rise VB until RESET goes to low
VMPon VBon
2.65
2.75 3.2
2.85
V V
VMP decreasing
Power-off Reset VL = 0, VMP = 3.3 V, VB = 0 V
Decrease VMP until INT returns to high
VLVI
2.5
2.6
2.7
V
Low-voltage reset Difference voltage between lowvoltage interrupt and reset
Logical Part VMP = 3.3 V, VB = 5 V
Decrease VMP until RESET returns to low VLVI - VLVR
VLVR
2.35 100
2.45 150
2.55
V mV
Output impedance at OSCOUT Pins SCL, SDA (input mode) Input leakage current Pins INT, SDA (output mode) Low level High level 0 < Vi < VMP Output low (resistance to GND)
0.6 0.8 x VMP -1 150
0.9
1.2 0.2 x VMP 1
k V V A
230
350
Switch for Additional Impedance (Pin IMPSW) VMP = 3.3 V, VB = 3 V
Switch-off leakage current Resistance to GND Maximum current
0 < Vi < VMP IMPSW = 0 IMPSW = 1 IMPSW = 1
-0.5 50 -5
5 80 5
A
mA
AFS (Acoustic Feedback Suppression), IL = 14 mA, VGEN = 300 mV, ERX = ETX = ENMIC = ENSTBAL = I1O1 = I3O3 = 1, SL[0:1] = 0, LF[0:3] = 1, P[0:4] = 31, AGARX[0:2] = 0
Adjustment range of attenuation Attenuation of transmit gain Attenuation of speaker amplifier Note:
IL 15 mA IL 15 mA, IINLDT = 0 A IINLDR = 10 A IL 15 mA, IINLDT = 10 A IINLDR = 0 A
GT
0 47 47 50 50
50 53 53
dB dB dB
GSA
1. This is a space of time where the bus must be from data transmission and before a new transmission can be started
33
4666B-CORD-08/04
Electrical Characteristics (Continued)
f = 1 kHz, 0 dBm = 775 mVrms, IVMIC = 0.3 mA, IMP = 3 mA, RDC = 1.3 M, Tamb = 25C, Zear = 68 nF + 100 , RLS = 50 , ZM = 68 nF, resonator: f = 3.58 MHz, all bits in reset condition, unless otherwise specified.
Parameters Test Conditions
Symbol Min. Typ. Max. Unit
Supply Voltages, VMIC = 25 mV, Tamb = - 10 to + 60 C
VMP VMPS VMIC VB Maximum output power Threshold
IL = 14 mA, RDC = 680 k IMP = 3 mA IL = 100 mA, RDC = inf., IMP = 0 mA IL = 14 mA, RDC = 1.3 M IM = 700 A IB = +20 mA, IL = 0 mA VRING = 20.6 V ENSA = ENSAO = SE = 1 VRING: high to low low to high, RINGTH [0:3] = 0 low to high, RINGTH [0:3] = 15
VMP VMPS VMIC VB
3.1
3.3
3.5 5.5
V V V V
1.5 5.5
4 6.3
Ringing Power Converter, IMP = 1 mA, IM = 0 RIMPA = 500 k
PSA
15 7.4 6.0 19 0.8 4.6 6.7 21 1 5.8 7.4 23 1.2 7.0
mW V V V V k V
Adjustment steps threshold Input impedance Maximum input voltage
DRINGTH = 1 VRING = 30 V VRINGmax SDA, SCL, INT ViBUS SDA ISDA = 3 mA SCL
30
Serial Bus SCL, SDA, AS, VMP = 3.3 V, RSDA = RSCL = RINT = 12 k
Input voltage HIGH LOW Output voltage Acknowledge LOW Clock frequency Rise time SDA, SCL Fall time SDA, SCL Period of SCL HIGH LOW
Setup Time
3.0 0
VDD 1.5 0.4 100 1 300
V V V kHz s ns s s s ns s s s s
VO fSCL tr tf
HIGH LOW
tH tL tsSTA tsDAT tsSTOP twSTA thSTA thDAT
4.0 4.7 4.7 250 4.7 4.7 4.0 0
Start condition Data Stop condition Time space(1)
Hold Time
Start condition DATA Note:
1. This is a space of time where the bus must be from data transmission and before a new transmission can be started
34
U4091BM-N
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4666B-CORD-08/04
Test Circuits
Figure 22. Basic Test Circuit
sin PWL V + V 3.58 MHz 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 + V + PWL
A
V
44
43
42
41
23
U4091BM
1 9 10 10 C IND R CD V 50 V V V V
2
3
4
5
6 8
7
11 12
13 14
15
16
17
18
19
20
21
22
+
+
sin
sin
U4091BM-N
35
Figure 23. Test Circuit for Ringing
36
PWL PWL 3.58 MHz + + 40 39 38 36 37 35 34 33 32 31 30 29 28 27 26 25 24 23
U4091BM-N
U4091BM
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 BC 556 22 2.2 mH 68 nF V 50 V VB VB SD103A
44
43
42
41
1
2
3
4
4666B-CORD-08/04
U4091BM-N
Bus Timing
Figure 24. Bus Timing Diagram
SDA
twSTA t r
SCL
t f
thSTA
P
S
thSTA
t L
t hDAT
P = Stop, S = Start
tH
tsSTA
thDAT
tsSTOP
P
Ordering Information
Extended Type Number Package Remarks
U4091BM-NFN U4091BM-NFNG3 T4091N-DDB
SSO44 SSO44 Die
Tube Taped and reeled Die on foil
Package Information
Package SSO44
Dimensions in mm
18.05 17.80 9.15 8.65 7.50 7.30
2.35 0.3 0.8 16.8 44 23 0.25 0.10
0.25 10.50 10.20
technical drawings according to DIN specifications
1
22
37
4666B-CORD-08/04
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4666B-CORD-08/04

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